Integrated circuits are increasingly ubiquitous and are used in any number of products. These integrated circuits are being applied to perform an increasing numbers of tasks and as a consequence these integrated circuits are also becoming increasingly diverse and complex. With this increase in complexity comes a commensurate increase in the cost of building these integrated circuits.
As the cost of producing, masking and fabricating these integrated circuit becomes increasingly expensive, when designing microchips or other integrated circuits it is desired to ensure that the resulting design is free of bugs. Verification assures that an integrated circuit is designed as specified and the design functions as intended before the design is committed to fabrication. Consequently, as the functionality of the integrated circuits increases, a large part of the development cycle of a chip may comprise verification to ensure that no bugs exist in the design of the integrated circuit before the design is proved to manufacturing.
By the same token, however, the decreased lifecycle and product life of integrated circuits is driving a desire for a quick turnaround between the conception, design and production of an integrated circuit. Consequently, a tension exists between the desire to adequately test an integrated circuit design (which may be modeled in software such as Verilog, VHDL, RTL, another type of hardware description language (HDL) or the like) before the design is provided to manufacturing and the desire for reducing the time between design and production of integrated circuits.
What is desired, then, are systems and methods for the efficient verification of integrated circuits.